Trenched MISFETs using silicon carbide (SiC) involve high SiC breakdown field strength, which creates a high electric field in the gate insulating film at the bottom portion of the trench during the OFF time, and tends to destroy the gate insulating film.
Trenched MISFETs thus require lowering the electric field applied during the OFF time to the gate insulating film at the bottom portion of the trench. U.S. Pat. No. 6,180,958B1 (Patent Literature 1) addresses this issue by proposing a technique that relaxes the electric field with a p-type layer disposed immediately below the gate insulating film at the lower portion of the trench. With the p-type layer disposed immediately below the gate insulating film at the lower portion of the trench, the voltage resistance at the junction between the p-type layer and an n-type layer of a drift layer in the lower portion of the gate insulating film is maintained, and the gate insulating film remains reliable. Trenched MISFETs also involve high gate-drain capacitance (feedback capacitance) compared to DMIS (double diffused Metal Insulator Semiconductor) FETs. An increased feedback capacitance is not desirable as it lowers the switching rate, and causes a defect called breakthrough. Feedback capacitance can be reduced by forming a p-type layer at the lower portion of the trench as in Patent Literature 1.
Forming a p-type layer at the lower portion of the trench is thus effective at relaxing the applied electric field to the gate insulating film, and reducing the feedback capacitance.
However, a p-type layer disposed at the lower portion of the trench as in Patent Literature 1 inhibits the flow of carriers from the channel to the drain electrode during the ON time, and increases ON resistance. Japanese Patent No. 4577355 (Patent Literature 2) attempts to solve the tradeoff between the reliability of the gate insulating film and ON resistance with a structure that suppresses increase of ON resistance with an arch-shaped p-type layer that is closer at the central portion to the lower portion of the trench, and is farther away from the trench at the periphery portion.
JP-A-2009-260064 (Patent Literature 3) discloses disposing a p-type layer below the trench in a manner allowing the p-type layer to partially cross the lower portion of the trench. The applied OFF-time electric field to the gate insulating film is relaxed with the p-type layer that crosses portions of the trench lower portion.